A computer's operating system has several interfaces with other components of the computer and the operating system must correctly deal with these interfaces to carry out its functions. One interface is between the operating system and the application programs, and is commonly known as the Application Programming interface (API). Other interfaces include those between the drivers, the memory management unit, the scheduler, and the instruction set architecture (ISA) of the underlying machine. Of these, a change to a different ISA poses difficulties for the operating system, as the operating system generally relies on certain features in the ISA to carry out its functions. One such feature of an ISA is how it handles interrupts, including non-maskable interrupts (NMIs). NMIs are frequently used by the operating system for implementing translation look-aside buffer (TLB) maintenance, for deadlock detection, and for servicing performance monitor counter overflows.
An NMI has certain properties including the following. An NMI should be deliverable during servicing of regular interrupts. An NMI should have higher priority than a regular interrupt. An NMI should be deliverable when regular interrupts are masked. An NMI should not be maskable (i.e., preventable), except under special circumstances. An NMI should be deliverable to an arbitrary CPU and as an inter-processor interrupt (IPI). Finally, an NMI should be deliverable as an arbitrary regular interrupt.
While the x86 ISA is a popular instruction set architecture, the ARM®64 processor and its ISA is becoming increasing popular, especially as processors embedded in mobile devices and IO devices. Devices, such as The ARM®64 Cortex®-A57 commercially available from ARM Holdings of Cambridge, United Kingdom, are multi-core processors with an integral generic interrupt controller (GIC), which offloads certain interrupt processing functions from the ARM processor cores. The GIC receives interrupts from the external world or from software and distributes a regular interrupt request (IRQ) and a fast interrupt request (FIQ) to the one or more of the ARM®64 processor cores. However, the ARM®64 core ISA and the GIC have no concept of an NMI.